In a power semiconductor device, a chip area is increased as a usual practice to increase a current capacity. However, since a crystal defect density in a substrate cannot be sufficiently decreased yet in a silicon carbide semiconductor device, when increasing a chip area, a considerable decrease in yield occurs. For this reason, devices with large current capacity are difficult to be manufactured at a high yield.
Relationships between a crystal defect and electric characteristics of a semiconductor device have been examined for a long time. However, particularly in a compound semiconductor such as a silicon carbide (SiC) semiconductor device, various types of defects such as a point defect, a complex defect, dislocation, extended dislocation, and a stacking fault occur. The so-called electric characteristics include various defective modes. At present, distinct one by one relationships between a crystal defect and electric characteristics cannot be easily obtained.
It is reported that a pit formed during formation of a thick oxide film on a silicon carbide semiconductor device deteriorates the reliability of an insulating film of a MOSFET (Y. Nakano, T. Nakamura, A. Kamisawa and H. Takasu, “Investigation of Pits Formed at Oxidation on 4H—SiC”, Material Science Forums Vols. 600-603 (2009) pp. 377 to 380).